A simple logic gate which employs enhancement mode switching FETs comprises an enhancement mode switching FET connected in series with a depletion mode load FET between two voltage supply terminals, an input terminal connected to the gate of the switching FET and an output terminal connected between the switching FET and the load FET. This logic gate operates as an invertor. If additional switching FETs are connected in parallel with the first switching FET and a corresponding input terminal is connected to the gate of each switching FET, a simple NOR gate is obtained. Circuits made up of such simple logic gates are known as Direct Coupled FET Logic (DCFL) circuits.
In order to function properly, DCFL logic circuits must be designed such that the output "logic low" level is below the threshold voltage of the enhancement mode switching FETs. While this may be relatively easy to achieve for silicon FETs which typically have threshold voltages of a few volts, it is more difficult to achieve for GaAs MESFETs which typically have threshold voltages which are an order of magnitude smaller. Moreover, because the threshold voltage is small, the noise margin of the "logic low" level is also small.
The "logic high" level of a DCFL logic gate is limited by the output current which flows into downstream logic gates. Thus, a DCFL logic gate which is connected to several downstream logic gates in parallel may have a "logic high" level which is close to its "logic low" level. In this case, noise margin of the "logic high" level will also be small.
The noise margins of DCFL gates can be improved by adding a level shifting buffer stage at the output of each gate. The level shifting buffer stage shifts the output level lower to improve the noise margin of the "logic low" level, and buffers the output to reduce the impact of fanout on the "logic high" level. However, the level shifting buffer stage significantly increases the power consumption of the logic gate. Thus, the improved noise margins are achieved at the expense of a significant power consumption penalty. Moreover, most known level shifting buffer stages require a supply voltage which differs from the supply voltages applied to the switching stage. The requirement for a third supply voltage complicates the design and increases the cost of circuits employing buffered gates.